Datasheet

Flash Memory Registers www.ti.com
7.4.1 FCTL1, Flash Memory Control Register
15 14 13 12 11 10 9 8
FRKEY, Read as 096h
FWKEY, Must be written as 0A5h
7 6 5 4 3 2 1 0
BLKWRT WRT Reserved EEIEX
(1)
EEI
(1)
MERAS ERASE Reserved
rw-0 rw-0 r0 rw-0 rw-0 rw-0 rw-0 r0
FRKEY Bits 15-8 FCTLx password. Always reads as 096h. Must be written as 0A5h. Writing any other value generates a PUC.
FWKEY
BLKWRT Bit 7 Block write mode. WRT must also be set for block write mode. BLKWRT is automatically reset when EMEX is
set.
0 Block-write mode is off
1 Block-write mode is on
WRT Bit 6 Write. This bit is used to select any write mode. WRT is automatically reset when EMEX is set.
0 Write mode is off
1 Write mode is on
Reserved Bit 5 Reserved. Always read as 0.
EEIEX Bit 4 Enable Emergency Interrupt Exit. Setting this bit enables an interrupt to cause an emergency exit from a flash
operation when GIE = 1. EEIEX is automatically reset when EMEX is set.
0 Exit interrupt disabled.
1 Exit on interrupt enabled.
EEI Bits 3 Enable Erase Interrupts. Setting this bit allows a segment erase to be interrupted by an interrupt request.
After the interrupt is serviced the erase cycle is resumed.
0 Interrupts during segment erase disabled.
1 Interrupts during segment erase enabled.
MERAS Bit 2 Mass erase and erase. These bits are used together to select the erase mode. MERAS and ERASE are
ERASE Bit 1 automatically reset when EMEX is set.
MERAS ERASE Erase Cycle
0 0 No erase
0 1 Erase individual segment only
1 0 Erase all main memory segments
1 1 LOCKA = 0: Erase main and information flash memory.
LOCKA = 1: Erase only main flash memory.
Reserved Bit 0 Reserved. Always read as 0.
(1)
Not present on MSP430x20xx and MSP430G2xx devices.
7.4.2 FCTL2, Flash Memory Control Register
15 14 13 12 11 10 9 8
FWKEYx, Read as 096h
Must be written as 0A5h
7 6 5 4 3 2 1 0
FSSELx FNx
rw-0 rw-1 rw-0 rw-0 rw-0 rw-0 rw-1 rw-0
FWKEYx Bits 15-8 FCTLx password. Always reads as 096h. Must be written as 0A5h. Writing any other value generates a PUC.
FSSELx Bits 7-6 Flash controller clock source select
00 ACLK
01 MCLK
10 SMCLK
11 SMCLK
FNx Bits 5-0 Flash controller clock divider. These six bits select the divider for the flash controller clock. The divisor value
is FNx + 1. For example, when FNx = 00h, the divisor is 1. When FNx = 03Fh, the divisor is 64.
324
Flash Memory Controller SLAU144J–December 2004–Revised July 2013
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