Datasheet
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Flash Memory Operation
The watchdog timer (in watchdog mode) should be disabled before a flash erase cycle. A reset aborts the
erase and the results are unpredictable. After the erase cycle has completed, the watchdog may be re-
enabled.
7.3.5 Stopping a Write or Erase Cycle
Any write or erase operation can be stopped before its normal completion by setting the emergency exit
bit EMEX. Setting the EMEX bit stops the active operation immediately and stops the flash controller. All
flash operations cease, the flash returns to read mode, and all bits in the FCTL1 register are reset. The
result of the intended operation is unpredictable.
7.3.6 Marginal Read Mode
The marginal read mode can be used to verify the integrity of the flash memory contents. This feature is
implemented in selected 2xx devices; see the device-specific data sheet for availability. During marginal
read mode marginally programmed flash memory bit locations can be detected. Events that could produce
this situation include improper f
FTG
settings, or violation of minimum V
CC
during erase or program
operations. One method for identifying such memory locations would be to periodically perform a
checksum calculation over a section of flash memory (for example, a flash segment) and repeating this
procedure with the marginal read mode enabled. If they do not match, it could indicate an insufficiently
programmed flash memory location. It is possible to refresh the affected Flash memory segment by
disabling marginal read mode, copying to RAM, erasing the flash segment, and writing back to it from
RAM.
The program checking the flash memory contents must be executed from RAM. Executing code from flash
automatically disables the marginal read mode. The marginal read modes are controlled by the MRG0 and
MRG1 register bits. Setting MRG1 is used to detect insufficiently programmed flash cells containing a 1
(erased bits). Setting MRG0 is used to detect insufficiently programmed flash cells containing a 0
(programmed bits). Only one of these bits should be set at a time. Therefore, a full marginal read check
requires two passes of checking the flash memory content's integrity. During marginal read mode, the
flash access speed (MCLK) must be limited to 1 MHz (see the device-specific data sheet).
7.3.7 Configuring and Accessing the Flash Memory Controller
The FCTLx registers are 16-bit password-protected read/write registers. Any read or write access must
use word instructions and write accesses must include the write password 0A5h in the upper byte. Any
write to any FCTLx register with any value other than 0A5h in the upper byte is a security key violation,
sets the KEYV flag and triggers a PUC system reset. Any read of any FCTLx registers reads 096h in the
upper byte.
Any write to FCTL1 during an erase or byte or word write operation is an access violation and sets
ACCVIFG. Writing to FCTL1 is allowed in block write mode when WAIT = 1, but writing to FCTL1 in block
write mode when WAIT = 0 is an access violation and sets ACCVIFG.
Any write to FCTL2 when the BUSY = 1 is an access violation.
Any FCTLx register may be read when BUSY = 1. A read does not cause an access violation.
7.3.8 Flash Memory Controller Interrupts
The flash controller has two interrupt sources, KEYV, and ACCVIFG. ACCVIFG is set when an access
violation occurs. When the ACCVIE bit is re-enabled after a flash write or erase, a set ACCVIFG flag
generates an interrupt request. ACCVIFG sources the NMI interrupt vector, so it is not necessary for GIE
to be set for ACCVIFG to request an interrupt. ACCVIFG may also be checked by software to determine if
an access violation occurred. ACCVIFG must be reset by software.
The key violation flag KEYV is set when any of the flash control registers are written with an incorrect
password. When this occurs, a PUC is generated immediately resetting the device.
7.3.9 Programming Flash Memory Devices
There are three options for programming an MSP430 flash device. All options support in-system
programming:
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SLAU144J–December 2004–Revised July 2013 Flash Memory Controller
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