Datasheet

Flash Memory Operation www.ti.com
; Write one block starting at 0F000h.
; Must be executed from RAM, Assumes Flash is already erased.
; 514 kHz < SMCLK < 952 kHz
; Assumes ACCVIE = NMIIE = OFIE = 0.
MOV #32,R5 ; Use as write counter
MOV #0F000h,R6 ; Write pointer
MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT
L1 BIT #BUSY,&FCTL3 ; Test BUSY
JNZ L1 ; Loop while busy
MOV #FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2
MOV #FWKEY,&FCTL3 ; Clear LOCK
MOV #FWKEY+BLKWRT+WRT,&FCTL1 ; Enable block write
L2 MOV Write_Value,0(R6) ; Write location
L3 BIT #WAIT,&FCTL3 ; Test WAIT
JZ L3 ; Loop while WAIT = 0
INCD R6 ; Point to next word
DEC R5 ; Decrement write counter
JNZ L2 ; End of block?
MOV #FWKEY,&FCTL1 ; Clear WRT,BLKWRT
L4 BIT #BUSY,&FCTL3 ; Test BUSY
JNZ L4 ; Loop while busy
MOV #FWKEY+LOCK,&FCTL3 ; Set LOCK
... ; Re-enable WDT if needed
7.3.4 Flash Memory Access During Write or Erase
When any write or any erase operation is initiated from RAM and while BUSY = 1, the CPU may not read
or write to or from any flash location. Otherwise, an access violation occurs, ACCVIFG is set, and the
result is unpredictable. Also if a write to flash is attempted with WRT = 0, the ACCVIFG interrupt flag is
set, and the flash memory is unaffected.
When a byte or word write or any erase operation is initiated from within flash memory, the flash controller
returns op-code 03FFFh to the CPU at the next instruction fetch. Op-code 03FFFh is the JMP PC
instruction. This causes the CPU to loop until the flash operation is finished. When the operation is
finished and BUSY = 0, the flash controller allows the CPU to fetch the proper op-code and program
execution resumes.
The flash access conditions while BUSY = 1 are listed in Table 7-3.
Table 7-3. Flash Access While BUSY = 1
Flash Operation Flash Access WAIT Result
Read 0 ACCVIFG = 0. 03FFFh is the value read.
Any erase, or
Write 0 ACCVIFG = 1. Write is ignored.
byte or word write
Instruction fetch 0 ACCVIFG = 0. CPU fetches 03FFFh. This is the JMP PC instruction.
Any 0 ACCVIFG = 1, LOCK = 1
Read 1 ACCVIFG = 0. 03FFFh is the value read.
Block write
Write 1 ACCVIFG = 0. Write is written.
Instruction fetch 1 ACCVIFG = 1, LOCK = 1
Interrupts are automatically disabled during any flash operation when EEI = 0 and EEIEX = 0 and on
MSP430x20xx and MSP430G2xx devices where EEI and EEIEX are not present. After the flash operation
has completed, interrupts are automatically re-enabled. Any interrupt that occurred during the operation
has its associated flag set and generates an interrupt request when re-enabled.
When EEIEX = 1 and GIE = 1, an interrupt immediately aborts any flash operation and the FAIL flag is
set. When EEI = 1, GIE = 1, and EEIEX = 0, a segment erase is interrupted by a pending interrupt every
32 f
FTG
cycles. After servicing the interrupt, the segment erase is continued for at least 32 f
FTG
cycles or
until it is complete. During the servicing of the interrupt, the BUSY bit remains set but the flash memory
can be accessed by the CPU without causing an access violation occurs. Nested interrupts and using the
RETI instruction inside interrupt service routines are not supported.
320
Flash Memory Controller SLAU144J–December 2004–Revised July 2013
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