Datasheet

Setup flash controller and erase

mode

Disable watchdog

Set LOCK=1, re-enable watchdog

Dummy write

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Flash Memory Operation

7.3.2.1 Initiating an Erase from Within Flash Memory

Any erase cycle can be initiated from within flash memory or from RAM. When a flash segment erase

operation is initiated from within flash memory, all timing is controlled by the flash controller, and the CPU

is held while the erase cycle completes. After the erase cycle completes, the CPU resumes code

execution with the instruction following the dummy write.

When initiating an erase cycle from within flash memory, it is possible to erase the code needed for

execution after the erase. If this occurs, CPU execution is unpredictable after the erase cycle.

The flow to initiate an erase from flash is shown in Figure 7-5.

Figure 7-5. Erase Cycle from Within Flash Memory

; Segment Erase from flash. 514 kHz < SMCLK < 952 kHz

; Assumes ACCVIE = NMIIE = OFIE = 0.

MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT

MOV #FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2

MOV #FWKEY, &FCTL3 ; Clear LOCK

MOV #FWKEY+ERASE, &FCTL1 ; Enable segment erase

CLR &0FC10h ; Dummy write, erase S1

MOV #FWKEY+LOCK, &FCTL3 ; Done, set LOCK

... ; Re-enable WDT?

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SLAU144J–December 2004–Revised July 2013 Flash Memory Controller

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