Datasheet

BUSY
Erase Operation Active
t
mass erase
= 10593/f
FTG
, t
segment erase
= 4819/f
FTG
Erase Time, V
CC
Current Consumption is Increased
Generate
Programming Voltage
Remove
Programming Voltage
Flash Memory Operation www.ti.com
7.3.2 Erasing Flash Memory
The erased level of a flash memory bit is 1. Each bit can be programmed from 1 to 0 individually but to
reprogram from 0 to 1 requires an erase cycle. The smallest amount of flash that can be erased is a
segment. There are three erase modes selected with the ERASE and MERAS bits listed in Table 7-1.
Table 7-1. Erase Modes
MERAS ERASE Erase Mode
0 1 Segment erase
1 0 Mass erase (all main memory segments)
LOCKA = 0: Erase main and information flash memory.
1 1
LOCKA = 1: Erase only main flash memory.
Any erase is initiated by a dummy write into the address range to be erased. The dummy write starts the
flash timing generator and the erase operation. Figure 7-4 shows the erase cycle timing. The BUSY bit is
set immediately after the dummy write and remains set throughout the erase cycle. BUSY, MERAS, and
ERASE are automatically cleared when the cycle completes. The erase cycle timing is not dependent on
the amount of flash memory present on a device. Erase cycle times are equivalent for all MSP430F2xx
and MSP430G2xx devices.
Figure 7-4. Erase Cycle Timing
A dummy write to an address not in the range to be erased does not start the erase cycle, does not affect
the flash memory, and is not flagged in any way. This errant dummy write is ignored.
312
Flash Memory Controller SLAU144J–December 2004–Revised July 2013
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