Datasheet

FN5 FN0
PUC
...........
EMEX
Flash Timing Generator
Divider, 1−64
BUSY WAIT
Reset
f
FTG
FSSELx
SMCLK
SMCLK
ACLK
MCLK
00
01
10
11
www.ti.com Flash Memory Operation
7.3 Flash Memory Operation
The default mode of the flash memory is read mode. In read mode, the flash memory is not being erased
or written, the flash timing generator and voltage generator are off, and the memory operates identically to
ROM.
MSP430 flash memory is in-system programmable (ISP) without the need for additional external voltage.
The CPU can program its own flash memory. The flash memory write and erase modes are selected with
the BLKWRT, WRT, MERAS, and ERASE bits and are:
• Byte or word write
• Block write
• Segment erase
• Mass erase (all main memory segments)
• All erase (all segments)
Reading from or writing to flash memory while it is being programmed or erased is prohibited. If CPU
execution is required during the write or erase, the code to be executed must be in RAM. Any flash update
can be initiated from within flash memory or RAM.
7.3.1 Flash Memory Timing Generator
Write and erase operations are controlled by the flash timing generator shown in Figure 7-3. The flash
timing generator operating frequency, f
FTG
, must be in the range from approximately 257 kHz to
approximately 476 kHz (see device-specific data sheet).
Figure 7-3. Flash Memory Timing Generator Block Diagram
7.3.1.1 Flash Timing Generator Clock Selection
The flash timing generator can be sourced from ACLK, SMCLK, or MCLK. The selected clock source
should be divided using the FNx bits to meet the frequency requirements for f
FTG
. If the f
FTG
frequency
deviates from the specification during the write or erase operation, the result of the write or erase may be
unpredictable, or the flash memory may be stressed above the limits of reliable operation.
If a clock failure is detected during a write or erase operation, the operation is aborted, the FAIL flag is set,
and the result of the operation is unpredictable.
While a write or erase operation is active the selected clock source can not be disabled by putting the
MSP430 into a low-power mode. The selected clock source remains active until the operation is
completed before being disabled.
311
SLAU144J–December 2004–Revised July 2013 Flash Memory Controller
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated