Datasheet

Bus

Grant

Module

WDT

Timer

Module

1 2 1 2 1 2 1 2 1

NMIRS

GIE

CPU

OSCfault

Reset/NMI

PUC

Circuit

PUC

WDT Security Key

Priority

High

Low

MAB − 5LSBs

GMIRS

Flash Security Key

Flash ACCV

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Interrupts

2.2 Interrupts

The interrupt priorities are fixed and defined by the arrangement of the modules in the connection chain as

shown in Figure 2-3. The nearer a module is to the CPU/NMIRS, the higher the priority. Interrupt priorities

determine what interrupt is taken when more than one interrupt is pending simultaneously.

There are three types of interrupts:

• System reset

• (Non)-maskable NMI

• Maskable

Figure 2-3. Interrupt Priority

2.2.1 (Non)-Maskable Interrupts (NMI)

(Non)-maskable NMI interrupts are not masked by the general interrupt enable bit (GIE), but are enabled

by individual interrupt enable bits (NMIIE, ACCVIE, OFIE). When a NMI interrupt is accepted, all NMI

interrupt enable bits are automatically reset. Program execution begins at the address stored in the (non)-

maskable interrupt vector, 0FFFCh. User software must set the required NMI interrupt enable bits for the

interrupt to be re-enabled. The block diagram for NMI sources is shown in Figure 2-4.

A (non)-maskable NMI interrupt can be generated by three sources:

• An edge on the RST/NMI pin when configured in NMI mode

• An oscillator fault occurs

• An access violation to the flash memory

SLAU144J–December 2004–Revised July 2013 System Resets, Interrupts, and Operating Modes

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