Datasheet

Enable
Data Latch
Enable
Address
Latch
Address Latch Data Latch
MAB
MDB
FCTL1
FCTL2
FCTL3
Timing
Generator
Programming
Voltage
Generator
Flash
Memory
Array
FCTL4
www.ti.com Flash Memory Introduction
7.1 Flash Memory Introduction
The MSP430 flash memory is bit-, byte-, and word-addressable and programmable. The flash memory
module has an integrated controller that controls programming and erase operations. The controller has
four registers, a timing generator, and a voltage generator to supply program and erase voltages.
MSP430 flash memory features include:
• Internal programming voltage generation
• Bit, byte, or word programmable
• Ultralow-power operation
• Segment erase and mass erase
• Marginal 0 and marginal 1 read mode (optional, see the device-specific data sheet)
Figure 7-1 shows the block diagram of the flash memory and controller.
NOTE: Minimum V
CC
during flash write or erase
The minimum V
CC
voltage during a flash write or erase operation is 2.2 V. If V
CC
falls below
2.2 V during write or erase, the result of the write or erase is unpredictable.
Figure 7-1. Flash Memory Module Block Diagram
7.2 Flash Memory Segmentation
MSP430 flash memory is partitioned into segments. Single bits, bytes, or words can be written to flash
memory, but the segment is the smallest size of flash memory that can be erased.
The flash memory is partitioned into main and information memory sections. There is no difference in the
operation of the main and information memory sections. Code or data can be located in either section.
The differences between the two sections are the segment size and the physical addresses.
The information memory has four 64-byte segments. The main memory has one or more 512-byte
segments. See the device-specific data sheet for the complete memory map of a device.
The segments are further divided into blocks.
309
SLAU144J–December 2004–Revised July 2013 Flash Memory Controller
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