Datasheet

www.ti.com DMA Registers
6.3.7 DMAIV, DMA Interrupt Vector Register
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
r0 r0 r0 r0 r0 r0 r0 r0
7 6 5 4 3 2 1 0
0 0 0 0 DMAIVx 0
r0 r0 r0 r0 r--(0) r--(0) r--(0) r0
DMAIVx Bits 15-0 DMA interrupt vector value
DMAIV Interrupt Source Interrupt Flag Interrupt
Contents Priority
00h No interrupt pending -
02h DMA channel 0 DMA0IFG Highest
04h DMA channel 1 DMA1IFG
06h DMA channel 2 DMA2IFG
08h Reserved -
0Ah Reserved -
0Ch Reserved -
0Eh Reserved - Lowest
307
SLAU144J–December 2004–Revised July 2013 DMA Controller
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