Datasheet

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DMA Registers

DMAABORT Bit 1 DMA Abort. This bit indicates if a DMA transfer was interrupt by an NMI.

0 DMA transfer not interrupted

1 DMA transfer was interrupted by NMI

DMAREQ Bit 0 DMA request. Software-controlled DMA start. DMAREQ is reset automatically.

0 No DMA start

1 Start DMA

6.3.4 DMAxSA, DMA Source Address Register

15 14 13 12 11 10 9 8

Reserved

r0 r0 r0 r0 r0 r0 r0 r0

7 6 5 4 3 2 1 0

Reserved DMAxSAx

r0 r0 r0 r0 rw rw rw rw

15 14 13 12 11 10 9 8

DMAxSAx

rw rw rw rw rw rw rw rw

7 6 5 4 3 2 1 0

DMAxSAx

rw rw rw rw rw rw rw rw

DMAxSA Bits 15-0

DMA source address

The source address register points to the DMA source address for single transfers or the first source

address for block transfers. The source address register remains unchanged during block and burst-block

transfers.

Devices that have addressable memory range 64 KB or below contain a single word for the DMAxSA. The

upper word is automatically cleared when writing using word operations. Reads from this location are always

read as zero.

Devices that have addressable memory range beyond 64 KB contain an additional word for the source

address. Bits 15-4 of this additional word are reserved and always read as zero. When writing to DMAxSA

with word formats, this additional word is automatically cleared. Reads of this additional word using word

formats, are always read as zero.

305

SLAU144J–December 2004–Revised July 2013 DMA Controller

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