Datasheet

DMA Registers www.ti.com
6.3.3 DMAxCTL, DMA Channel x Control Register
15 14 13 12 11 10 9 8
Reserved DMADTx DMADSTINCRx DMASRCINCRx
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
7 6 5 4 3 2 1 0
DMADST DMASRC DMALEVEL DMAEN DMAIFG DMAIE DMAABORT DMAREQ
BYTE BYTE
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
Reserved Bit 15 Reserved
DMADTx Bits 14-12 DMA Transfer mode.
000 Single transfer
001 Block transfer
010 Burst-block transfer
011 Burst-block transfer
100 Repeated single transfer
101 Repeated block transfer
110 Repeated burst-block transfer
111 Repeated burst-block transfer
DMADSTINCRx Bits 11-10 DMA destination increment. This bit selects automatic incrementing or decrementing of the
destination address after each byte or word transfer. When DMADSTBYTE = 1, the destination
address increments/decrements by one. When DMADSTBYTE = 0, the destination address
increments/decrements by two. The DMAxDA is copied into a temporary register and the
temporary register is incremented or decremented. DMAxDA is not incremented or decremented.
00 Destination address is unchanged
01 Destination address is unchanged
10 Destination address is decremented
11 Destination address is incremented
DMASRCINCRx Bits 9-8 DMA source increment. This bit selects automatic incrementing or decrementing of the source
address for each byte or word transfer. When DMASRCBYTE = 1, the source address
increments/decrements by one. When DMASRCBYTE = 0, the source address
increments/decrements by two. The DMAxSA is copied into a temporary register and the
temporary register is incremented or decremented. DMAxSA is not incremented or decremented.
00 Source address is unchanged
01 Source address is unchanged
10 Source address is decremented
11 Source address is incremented
DMADSTBYTE Bit 7 DMA destination byte. This bit selects the destination as a byte or word.
0 Word
1 Byte
DMASRCBYTE Bit 6 DMA source byte. This bit selects the source as a byte or word.
0 Word
1 Byte
DMALEVEL Bit 5 DMA level. This bit selects between edge-sensitive and level-sensitive triggers.
0 Edge sensitive (rising edge)
1 Level sensitive (high level)
DMAEN Bit 4 DMA enable
0 Disabled
1 Enabled
DMAIFG Bit 3 DMA interrupt flag
0 No interrupt pending
1 Interrupt pending
DMAIE Bit 2 DMA interrupt enable
0 Disabled
1 Enabled
304
DMA Controller SLAU144J–December 2004–Revised July 2013
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