Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TSSOP 28 16-Bit 16 MHz I/O number 24

301

302

303

304

305

306

307

308

309

310

www.ti.com

DMA Registers

6.3.1 DMACTL0, DMA Control Register 0

15 14 13 12 11 10 9 8

Reserved DMA2TSELx

rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)

7 6 5 4 3 2 1 0

DMA1TSELx DMA0TSELx

rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)

Reserved Bits 15-12 Reserved

DMA2TSELx Bits 11-8 DMA trigger select. These bits select the DMA transfer trigger.

0000 DMAREQ bit (software trigger)

0001 TACCR2 CCIFG bit

0010 TBCCR2 CCIFG bit

0011 Serial data received UCA0RXIFG

0100 Serial data transmit ready UCA0TXIFG

0101 DAC12_0CTL DAC12IFG bit

0110 ADC12 ADC12IFGx bit

0111 TACCR0 CCIFG bit

1000 TBCCR0 CCIFG bit

1001 Serial data received UCA1RXIFG

1010 Serial data transmit ready UCA1TXIFG

1011 Multiplier ready

1100 Serial data received UCB0RXIFG

1101 Serial data transmit ready UCB0TXIFG

1110 DMA0IFG bit triggers DMA channel 1

DMA1IFG bit triggers DMA channel 2

DMA2IFG bit triggers DMA channel 0

1111 External trigger DMAE0

DMA1TSELx Bits 7-4 Same as DMA2TSELx

DMA0TSELx Bits 3-0 Same as DMA2TSELx

6.3.2 DMACTL1, DMA Control Register 1

15 14 13 12 11 10 9 8

0 0 0 0 0 0 0 0

r0 r0 r0 r0 r0 r0 r0 r0

7 6 5 4 3 2 1 0

0 0 0 0 0 DMAON ROUND ENNMI

FETCH ROBIN

r0 r0 r0 r0 r0 rw-(0) rw-(0) rw-(0)

Reserved Bits 15-3 Reserved. Read only. Always read as 0.

DMAONFETCH Bit 2 DMA on fetch

0 The DMA transfer occurs immediately.

1 The DMA transfer occurs on next instruction fetch after the trigger.

ROUNDROBIN Bit 1 Round robin. This bit enables the round-robin DMA channel priorities.

0 DMA channel priority is DMA0 - DMA1 - DMA2

1 DMA channel priority changes with each transfer

ENNMI Bit 0 Enable NMI. This bit enables the interruption of a DMA transfer by an NMI interrupt. When an NMI

interrupts a DMA transfer, the current transfer is completed normally, further transfers are stopped, and

DMAABORT is set.

0 NMI interrupt does not interrupt DMA transfer

1 NMI interrupt interrupts a DMA transfer

303

SLAU144J–December 2004–Revised July 2013 DMA Controller

Submit Documentation Feedback