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6.3 DMA Registers
The DMA registers are listed in Table 6-5.
Table 6-5. DMA Registers
Register Short Form Register Type Address Initial State
DMA control 0 DMACTL0 Read/write 0122h Reset with POR
DMA control 1 DMACTL1 Read/write 0124h Reset with POR
DMA interrupt vector DMAIV Read only 0126h Reset with POR
DMA channel 0 control DMA0CTL Read/write 01D0h Reset with POR
DMA channel 0 source address DMA0SA Read/write 01D2h Unchanged
DMA channel 0 destination address DMA0DA Read/write 01D6h Unchanged
DMA channel 0 transfer size DMA0SZ Read/write 01DAh Unchanged
DMA channel 1 control DMA1CTL Read/write 01DCh Reset with POR
DMA channel 1 source address DMA1SA Read/write 01DEh Unchanged
DMA channel 1 destination address DMA1DA Read/write 01E2h Unchanged
DMA channel 1 transfer size DMA1SZ Read/write 01E6h Unchanged
DMA channel 2 control DMA2CTL Read/write 01E8h Reset with POR
DMA channel 2 source address DMA2SA Read/write 01EAh Unchanged
DMA channel 2 destination address DMA2DA Read/write 01EEh Unchanged
DMA-channel 2 transfer size DMA2SZ Read/write 01F2h Unchanged
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DMA Controller SLAU144J–December 2004–Revised July 2013
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