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6.2.8 DMA Controller Interrupts
Each DMA channel has its own DMAIFG flag. Each DMAIFG flag is set in any mode, when the
corresponding DMAxSZ register counts to zero. If the corresponding DMAIE and GIE bits are set, an
interrupt request is generated.
All DMAIFG flags source only one DMA controller interrupt vector and, on some devices, the interrupt
vector may be shared with other modules. Please refer to the device specific datasheet for further details.
For these devices, software must check the DMAIFG and respective module flags to determine the source
of the interrupt. The DMAIFG flags are not reset automatically and must be reset by software.
Additionally, some devices utilize the DMAIV register. All DMAIFG flags are prioritized, with DMA0IFG
being the highest, and combined to source a single interrupt vector. The highest priority enabled interrupt
generates a number in the DMAIV register. This number can be evaluated or added to the program
counter to automatically enter the appropriate software routine. Disabled DMA interrupts do not affect the
DMAIV value.
Any access, read or write, of the DMAIV register automatically resets the highest pending interrupt flag. If
another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt.
For example, assume that DMA0 has the highest priority. If the DMA0IFG and DMA2IFG flags are set
when the interrupt service routine accesses the DMAIV register, DMA0IFG is reset automatically. After the
RETI instruction of the interrupt service routine is executed, the DMA2IFG will generate another interrupt.
The following software example shows the recommended use of DMAIV and the handling overhead. The
DMAIV value is added to the PC to automatically jump to the appropriate routine.
The numbers at the right margin show the necessary CPU cycles for each instruction. The software
overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not
the task handling itself.
Example 6-1. DMAIV Software Example
;Interrupt handler for DMA0IFG, DMA1IFG, DMA2IFG Cycles
DMA_HND ... ; Interrupt latency 6
ADD &DMAIV,PC ; Add offset to Jump table 3
RETI ; Vector 0: No interrupt 5
JMP DMA0_HND ; Vector 2: DMA channel 0 2
JMP DMA1_HND ; Vector 4: DMA channel 1 2
JMP DMA2_HND ; Vector 6: DMA channel 2 2
RETI ; Vector 8: Reserved 5
RETI ; Vector 10: Reserved 5
RETI ; Vector 12: Reserved 5
RETI ; Vector 14: Reserved 5
DMA2_HND ; Vector 6: DMA channel 2
... ; Task starts here
RETI ; Back to main program 5
DMA1_HND ; Vector 4: DMA channel 1
... ; Task starts here
RETI ; Back to main program 5
DMA0_HND ; Vector 2: DMA channel 0
... ; Task starts here
RETI ; Back to main program 5
6.2.9 Using the USCI_B I
2
C Module with the DMA Controller
The USCI_B I
2
C module provides two trigger sources for the DMA controller. The USCI_B I
2
C module can
trigger a transfer when new I
2
C data is received and when data is needed for transmit.
A transfer is triggered if UCB0RXIFG is set. The UCB0RXIFG is cleared automatically when the DMA
controller acknowledges the transfer. If UCB0RXIE is set, UCB0RXIFG will not trigger a transfer.
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DMA Controller SLAU144J–December 2004–Revised July 2013
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