Datasheet

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6.2.5 DMA Channel Priorities
The default DMA channel priorities are DMA0-DMA1-DMA2. If two or three triggers happen
simultaneously or are pending, the channel with the highest priority completes its transfer (single, block or
burst-block transfer) first, then the second priority channel, then the third priority channel. Transfers in
progress are not halted if a higher priority channel is triggered. The higher priority channel waits until the
transfer in progress completes before starting.
The DMA channel priorities are configurable with the ROUNDROBIN bit. When the ROUNDROBIN bit is
set, the channel that completes a transfer becomes the lowest priority. The order of the priority of the
channels always stays the same, DMA0-DMA1-DMA2 (see Table 6-3).
Table 6-3. Channel Priorities
DMA Priority Transfer Occurs New DMA Priority
DMA0 - DMA1 - DMA2 DMA1 DMA2 - DMA0 - DMA1
DMA2 - DMA0 - DMA1 DMA2 DMA0 - DMA1 - DMA2
DMA0 - DMA1 - DMA2 DMA0 DMA1 - DMA2 - DMA0
When the ROUNDROBIN bit is cleared the channel priority returns to the default priority.
6.2.6 DMA Transfer Cycle Time
The DMA controller requires one or two MCLK clock cycles to synchronize before each single transfer or
complete block or burst-block transfer. Each byte/word transfer requires two MCLK cycles after
synchronization, and one cycle of wait time after the transfer. Because the DMA controller uses MCLK, the
DMA cycle time is dependent on the MSP430 operating mode and clock system setup.
If the MCLK source is active, but the CPU is off, the DMA controller will use the MCLK source for each
transfer, without re-enabling the CPU. If the MCLK source is off, the DMA controller will temporarily restart
MCLK, sourced with DCOCLK, for the single transfer or complete block or burst-block transfer. The CPU
remains off, and after the transfer completes, MCLK is turned off. The maximum DMA cycle time for all
operating modes is shown in Table 6-4.
Table 6-4. Maximum Single-Transfer DMA Cycle Time
CPU Operating Mode Clock Source Maximum DMA Cycle Time
Active mode MCLK = DCOCLK 4 MCLK cycles
Active mode MCLK = LFXT1CLK 4 MCLK cycles
Low-power mode LPM0/1 MCLK = DCOCLK 5 MCLK cycles
Low-power mode LPM3/4 MCLK = DCOCLK 5 MCLK cycles + 6 µs
(1)
Low-power mode LPM0/1 MCLK = LFXT1CLK 5 MCLK cycles
Low-power mode LPM3 MCLK = LFXT1CLK 5 MCLK cycles
Low-power mode LPM4 MCLK = LFXT1CLK 5 MCLK cycles + 6 µs
(1)
(1)
The additional 6 µs are needed to start the DCOCLK. It is the t
(LPMx)
parameter in the data sheet.
6.2.7 Using DMA With System Interrupts
DMA transfers are not interruptible by system interrupts. System interrupts remain pending until the
completion of the transfer. NMI interrupts can interrupt the DMA controller if the ENNMI bit is set.
System interrupt service routines are interrupted by DMA transfers. If an interrupt service routine or other
routine must execute with no interruptions, the DMA controller should be disabled prior to executing the
routine.
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SLAU144J–December 2004–Revised July 2013 DMA Controller
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