Datasheet

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6.2.3 Initiating DMA Transfers
Each DMA channel is independently configured for its trigger source with the DMAxTSELx bits as
described in Table 6-2. The DMAxTSELx bits should be modified only when the DMACTLx DMAEN bit is
0. Otherwise, unpredictable DMA triggers may occur.
When selecting the trigger, the trigger must not have already occurred, or the transfer will not take place.
For example, if the TACCR2 CCIFG bit is selected as a trigger, and it is already set, no transfer will occur
until the next time the TACCR2 CCIFG bit is set.
6.2.3.1 Edge-Sensitive Triggers
When DMALEVEL = 0, edge-sensitive triggers are used and the rising edge of the trigger signal initiates
the transfer. In single-transfer mode, each transfer requires its own trigger. When using block or burst-
block modes, only one trigger is required to initiate the block or burst-block transfer.
6.2.3.2 Level-Sensitive Triggers
When DMALEVEL = 1, level-sensitive triggers are used. For proper operation, level-sensitive triggers can
only be used when external trigger DMAE0 is selected as the trigger. DMA transfers are triggered as long
as the trigger signal is high and the DMAEN bit remains set.
The trigger signal must remain high for a block or burst-block transfer to complete. If the trigger signal
goes low during a block or burst-block transfer, the DMA controller is held in its current state until the
trigger goes back high or until the DMA registers are modified by software. If the DMA registers are not
modified by software, when the trigger signal goes high again, the transfer resumes from where it was
when the trigger signal went low.
When DMALEVEL = 1, transfer modes selected when DMADTx = {0, 1, 2, 3} are recommended because
the DMAEN bit is automatically reset after the configured transfer.
6.2.3.3 Halting Executing Instructions for DMA Transfers
The DMAONFETCH bit controls when the CPU is halted for a DMA transfer. When DMAONFETCH = 0,
the CPU is halted immediately and the transfer begins when a trigger is received. When DMAONFETCH =
1, the CPU finishes the currently executing instruction before the DMA controller halts the CPU and the
transfer begins.
NOTE: DMAONFETCH Must Be Used When The DMA Writes To Flash
If the DMA controller is used to write to flash memory, the DMAONFETCH bit must be set.
Otherwise, unpredictable operation can result.
Table 6-2. DMA Trigger Operation
DMAxTSELx Operation
0000 A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically reset when the transfer
starts
0001 A transfer is triggered when the TACCR2 CCIFG flag is set. The TACCR2 CCIFG flag is automatically reset
when the transfer starts. If the TACCR2 CCIE bit is set, the TACCR2 CCIFG flag will not trigger a transfer.
0010 A transfer is triggered when the TBCCR2 CCIFG flag is set. The TBCCR2 CCIFG flag is automatically reset
when the transfer starts. If the TBCCR2 CCIE bit is set, the TBCCR2 CCIFG flag will not trigger a transfer.
0011
A transfer is triggered when serial interface receives new data.
Devices with USCI_A0 module: A transfer is triggered when USCI_A0 receives new data. UCA0RXIFG is
automatically reset when the transfer starts. If UCA0RXIE is set, the UCA0RXIFG flag will not trigger a
transfer.
0100
A transfer is triggered when serial interface is ready to transmit new data.
Devices with USCI_A0 module: A transfer is triggered when USCI_A0 is ready to transmit new data.
UCA0TXIFG is automatically reset when the transfer starts. If UCA0TXIE is set, the UCA0TXIFG flag will not
trigger a transfer.
297
SLAU144J–December 2004–Revised July 2013 DMA Controller
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