Datasheet

Reset
Wait for Trigger
Idle
Hold CPU,
Transfer one word/byte
[+Trigger AND DMALEVEL = 0 ]
OR
[Trigger=1AND DMALEVEL=1]
DMAABORT=0
DMAABORT = 1
2 x MCLK
DMAEN = 0
Modify T_SourceAdd
Modify T_DestAdd
Decrement DMAxSZ
[ENNMI = 1
AND NMI event]
OR
[DMALEVEL = 1
AND Trigger = 0]
[ DMADTx = 0
AND DMAxSZ = 0]
OR DMAEN = 0
DMAxSZ → T_Size
DMAxSA → T_SourceAdd
DMAxDA → T_DestAdd
DMAREQ = 0
DMAxSZ > 0
AND DMAEN = 1
DMAEN = 0
DMAEN = 1
T_Size → DMAxSZ
DMAxSA → T_SourceAdd
DMAxDA → T_DestAdd
DMADTx = 4
AND DMAxSZ = 0
AND DMAEN = 1
DMAEN = 0
DMAREQ = 0
T_Size → DMAxSZ
DMA Operation www.ti.com
6.2.2.1 Single Transfer
In single transfer mode, each byte/word transfer requires a separate trigger. The single transfer state
diagram is shown in Figure 6-3.
The DMAxSZ register is used to define the number of transfers to be made. The DMADSTINCRx and
DMASRCINCRx bits select if the destination address and the source address are incremented or
decremented after each transfer. If DMAxSZ = 0, no transfers occur.
The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary registers. The temporary
values of DMAxSA and DMAxDA are incremented or decremented after each transfer. The DMAxSZ
register is decremented after each transfer. When the DMAxSZ register decrements to zero it is reloaded
from its temporary register and the corresponding DMAIFG flag is set. When DMADTx = 0, the DMAEN bit
is cleared automatically when DMAxSZ decrements to zero and must be set again for another transfer to
occur.
In repeated single transfer mode, the DMA controller remains enabled with DMAEN = 1, and a transfer
occurs every time a trigger occurs.
Figure 6-3. DMA Single Transfer State Diagram
292
DMA Controller SLAU144J–December 2004–Revised July 2013
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