Datasheet

ENNMI
DT
DMA Channel 2
DMASRSBYTE
DMA2SZ
DMA2DA
DMA2SA
DMADSTBYTE
DMASRCINCRx
DMADSTINCRx
2
2
3
DMADTx
DMAEN
DT
DMA Channel 1
DMASRSBYTE
DMA1SZ
DMA1DA
DMA1SA
DMADSTBYTE
DMASRCINCRx
DMADSTINCRx
2
2
3
DMADTx
DMAEN
DT
DMA Channel 0
DMASRSBYTE
DMA0SZ
DMA0DA
DMA0SA
DMADSTBYTE
DMASRCINCRx
DMADSTINCRx
2
2
3
DMADTx
DMAEN
Address
Space
NMI Interrupt Request
JTAG Active
Halt
Halt CPU
ROUNDROBIN
DMAONFETCH
DAC12_0IFG
DMAE0
DMAREQ
DMA0TSELx
4
DMA2IFG
TACCR2_CCIFG
TBCCR2_CCIFG
ADC12_IFGx
0000
0001
0010
0011
0100
0101
1101
1111
1110
0110
USCI A0 data receive
USCI A0 data transmit
1100
0111
USCI B0 data transmit
USCI B0 data receive
TACCR0_CCIFG
1000
TBCCR0_CCIFG
1010
1001
USCI A1 data Tx
USCI A1 data Rx
1011
Multiplier ready
DMA Priority And Controll
DAC12_0IFG
DMAE0
DMAREQ
DMA1TSELx
4
DMA0IFG
TACCR2_CCIFG
TBCCR2_CCIFG
ADC12_IFGx
0000
0001
0010
0011
0100
0101
1101
1111
1110
0110
1100
0111
TACCR0_CCIFG
1000
TBCCR0_CCIFG
1010
1001
1011
Multiplier ready
DAC12_0IFG
DMAE0
DMAREQ
DMA2TSEL
4
DMA1IFG
TACCR2_CCIFG
TBCCR2_CCIFG
ADC12_IFGx
0000
0001
0010
0011
0100
0101
1101
1111
1110
0110
1100
0111
TACCR0_CCIFG
1000
TBCCR0_CCIFG
1010
1001
1011
Multiplier ready
USCI A0 data receive
USCI A0 data transmit
USCI B0 data transmit
USCI B0 data receive
USCI A0 data receive
USCI A0 data transmit
USCI B0 data transmit
USCI B0 data receive
USCI A1 data Tx
USCI A1 data Rx
USCI A1 data Tx
USCI A1 data Rx
www.ti.com DMA Introduction
Figure 6-1. DMA Controller Block Diagram
289
SLAU144J–December 2004–Revised July 2013 DMA Controller
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