Datasheet

www.ti.com Basic Clock Module+ Registers
5.3.4 BCSCTL3, Basic Clock System Control Register 3
7 6 5 4 3 2 1 0
XT2Sx LFXT1Sx
(1)
XCAPx
(2)
XT2OF
(3)
LFXT1OF
(2)
rw-0 rw-0 rw-0 rw-0 rw-0 rw-1 r0 r-(1)
XT2Sx Bits 7-6 XT2 range select. These bits select the frequency range for XT2.
00 0.4- to 1-MHz crystal or resonator
01 1- to 3-MHz crystal or resonator
10 3- to 16-MHz crystal or resonator
11 Digital external 0.4- to 16-MHz clock source
LFXT1Sx Bits 5-4 Low-frequency clock select and LFXT1 range select. These bits select between LFXT1 and VLO when XTS =
0, and select the frequency range for LFXT1 when XTS = 1.
When XTS = 0:
00 32768-Hz crystal on LFXT1
01 Reserved
10 VLOCLK (Reserved in MSP430F21x1 devices)
11 Digital external clock source
When XTS = 1 (Not applicable for MSP430x20xx devices, MSP430G2xx1/2/3)
00 0.4- to 1-MHz crystal or resonator
01 1- to 3-MHz crystal or resonator
10 3- to 16-MHz crystal or resonator
11 Digital external 0.4- to 16-MHz clock source
LFXT1Sx definition for MSP430AFE2xx devices:
00 Reserved
01 Reserved
10 VLOCLK
11 Reserved
XCAPx Bits 3-2 Oscillator capacitor selection. These bits select the effective capacitance seen by the LFXT1 crystal when
XTS = 0. If XTS = 1 or if LFXT1Sx = 11 XCAPx should be 00.
00 ~1 pF
01 ~6 pF
10 ~10 pF
11 ~12.5 pF
XT2OF Bit 1 XT2 oscillator fault
0 No fault condition present
1 Fault condition present
LFXT1OF Bit 0 LFXT1 oscillator fault
0 No fault condition present
1 Fault condition present
(1)
MSP430G22x0: The LFXT1Sx bits should be programmed to 10b during the initialization and start-up code to select VLOCLK (for more
details refer to Digital I/O chapter). The other bits are reserved and should not be altered.
(2)
This bit is reserved in the MSP430AFE2xx devices.
(3)
Does not apply to MSP430x2xx, MSP430x21xx, or MSP430x22xx devices.
285
SLAU144J–December 2004–Revised July 2013 Basic Clock Module+
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