Datasheet

LF_OscFault
XT1_OscFault
XT2_OscFault
XTS
XT2OF
LFXT1OF
Set OFIFG Flag
Basic Clock Module+ Operation www.ti.com
• High-frequency oscillator fault (LFXT1OF) for LFXT1 in HF mode
• High-frequency oscillator fault (XT2OF) for XT2
The crystal oscillator fault bits LFXT1OF, and XT2OF are set if the corresponding crystal oscillator is
turned on and not operating properly. The fault bits remain set as long as the fault condition exists and are
automatically cleared if the enabled oscillators function normally.
The OFIFG oscillator-fault flag is set and latched at POR or when an oscillator fault (LFXT1OF, or XT2OF)
is detected. When OFIFG is set, MCLK is sourced from the DCO, and if OFIE is set, the OFIFG requests
an NMI interrupt. When the interrupt is granted, the OFIE is reset automatically. The OFIFG flag must be
cleared by software. The source of the fault can be identified by checking the individual fault bits.
If a fault is detected for the crystal oscillator sourcing the MCLK, the MCLK is automatically switched to
the DCO for its clock source. This does not change the SELMx bit settings. This condition must be
handled by user software.
Figure 5-8. Oscillator-Fault Logic
5.2.7.1 Sourcing MCLK from a Crystal
After a PUC, the basic clock module+ uses DCOCLK for MCLK. If required, MCLK may be sourced from
LFXT1 or XT2 - if available.
The sequence to switch the MCLK source from the DCO clock to the crystal clock (LFXT1CLK or
XT2CLK) is:
1. Turn on the crystal oscillator and select the appropriate mode
2. Clear the OFIFG flag
3. Wait at least 50 µs
4. Test OFIFG, and repeat steps 2 through 4 until OFIFG remains cleared.
; Select LFXT1 (HF mode) for MCLK
BIC.W #OSCOFF,SR ; Turn on osc.
BIS.B #XTS,&BCSCTL1 ; HF mode
MOV.B #LFXT1S0,&BCSCTL3 ; 1-3MHz Crystal
L1 BIC.B #OFIFG,&IFG1 ; Clear OFIFG
MOV.W #0FFh,R15 ; Delay
L2 DEC.W R15 ;
JNZ L2 ;
BIT.B #OFIFG,&IFG1 ; Re-test OFIFG
JNZ L1 ; Repeat test if needed
BIS.B #SELM1+SELM0,&BCSCTL2 ; Select LFXT1CLK
5.2.8 Synchronization of Clock Signals
When switching MCLK or SMCLK from one clock source to another, the switch is synchronized to avoid
critical race conditions as shown in Figure 5-9:
• The current clock cycle continues until the next rising edge.
• The clock remains high until the next rising edge of the new clock.
• The new clock source is selected and continues with a full high period.
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Basic Clock Module+ SLAU144J–December 2004–Revised July 2013
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