Datasheet

RSEL=0
RSEL = 15
DCO=0 DCO=7DCO=4DCO=1 DCO=2 DCO=3 DCO=5 DCO=6
f
DCO
20000 kHz
100 kHz
1000 kHz
RSEL = 7
MCLK_request
CPUOFF
SCG1
SELS
SMCLK_request
XSELM1
SYNC
DCOCLK
XT2CLK
QD
SCG0
DCOCLK_on
1: on
0: off
1: on
0: off
DCO_Gen_on
DCOCLK
Basic Clock Module+ Operation www.ti.com
Figure 5-5. On/Off Control of DCO
5.2.5.2 Adjusting the DCO Frequency
After a PUC, RSELx = 7 and DCOx = 3, allowing the DCO to start at a mid-range frequency. MCLK and
SMCLK are sourced from DCOCLK. Because the CPU executes code from MCLK, which is sourced from
the fast-starting DCO, code execution typically begins from PUC in less than 2 µs. The typical DCOx and
RSELx ranges and steps are shown in Figure 5-6.
The frequency of DCOCLK is set by the following functions:
• The four RSELx bits select one of sixteen nominal frequency ranges for the DCO. These ranges are
defined for an individual device in the device-specific data sheet.
• The three DCOx bits divide the DCO range selected by the RSELx bits into 8 frequency steps,
separated by approximately 10%.
• The five MODx bits, switch between the frequency selected by the DCOx bits and the next higher
frequency set by DCOx+1. When DCOx = 07h, the MODx bits have no effect because the DCO is
already at the highest setting for the selected RSELx range.
Figure 5-6. Typical DCOx Range and RSELx Steps
Each MSP430F2xx device (and most MSP430G2xx devices; see device-specific data sheets) has
calibrated DCOCTL and BCSCTL1 register settings for specific frequencies stored in information memory
segment A. To use the calibrated settings, the information is copied into the DCOCTL and BCSCTL1
registers. The calibrated settings affect the DCOx, MODx, and RSELx bits, and clear all other bits, except
XT2OFF which remains set. The remaining bits of BCSCTL1 can be set or cleared as needed with BIS.B
or BIC.B instructions.
; Set DCO to 1 MHz:
CLR.B &DCOCTL ; Select lowest DCOx
; and MODx settings
278
Basic Clock Module+ SLAU144J–December 2004–Revised July 2013
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