Datasheet

Divider
/1/2/4/8
DIVAx
MCLK
CPUOFF
DCOCLK
Divider
/1/2/4/8
DIVMx
SMCLK
SCG1
DIVSx
ACLK
Main System Clock
Auxillary Clock
Sub System Clock
DCO
DCOx
DC
Generator
SCG0 RSELx
off
SELS
1
0
SELMx
00
01
10
11
1
0
1
0
Divider
/1/2/4/8
Modulator
1
0
n
n+1
Min. Puls
Filter
MODx
else
10
Internal
LP/LF
VLOCLK
XT2IN
XT2OUT
XT2OFF
XT
Min. Pulse
Filter
XT2Sx
VCC
XT2 Oscillator
OSCOFF
LFXT1Sx
www.ti.com Basic Clock Module+ Operation
Figure 5-2. Basic Clock Module+ Block Diagram − MSP430AFE2xx
NOTE: LFXT1 is not present in MSP430AFE2xx devices.
5.2 Basic Clock Module+ Operation
After a PUC, MCLK and SMCLK are sourced from DCOCLK at ~1.1 MHz (see the device-specific data
sheet for parameters) and ACLK is sourced from LFXT1CLK in LF mode with an internal load capacitance
of 6 pF.
Status register control bits SCG0, SCG1, OSCOFF, and CPUOFF configure the MSP430 operating modes
and enable or disable portions of the basic clock module+ (see the System Resets, Interrupts and
Operating Modes chapter). The DCOCTL, BCSCTL1, BCSCTL2, and BCSCTL3 registers configure the
basic clock module+.
The basic clock module+ can be configured or reconfigured by software at any time during program
execution, for example:
CLR.B &DCOCTL ; Select lowest DCOx
; and MODx settings
BIS.B #RSEL2+RSEL1+RSEL0,&BCSCTL1 ; Select range 7
BIS.B #DCO2+DCO1+DCO0,&DCOCTL ; Select max DCO tap
275
SLAU144J–December 2004–Revised July 2013 Basic Clock Module+
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