Datasheet

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Instruction Set Description

4.6.4.11 SUBA

SUBA Subtract 20-bit source from 20-bit destination register

SUBA Rsrc,Rdst

Syntax

SUBA #imm20,Rdst

Operation (.not.src) + 1 + Rdst → Rdst or Rdst – src → Rdst

Description The 20-bit source operand is subtracted from the 20-bit destination register. This is

made by adding the 1s complement of the source + 1 to the destination. The result is

written to the destination register, the source is not affected.

Status Bits N: Set if result is negative (src > dst), reset if positive (src ≤ dst)

Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst)

C: Set if there is a carry from the MSB (Rdst.19), reset otherwise

V: Set if the subtraction of a negative source operand from a positive destination

operand delivers a negative result, or if the subtraction of a positive source

operand from a negative destination operand delivers a positive result, reset

otherwise (no overflow)

Mode Bits OSCOFF, CPUOFF, and GIE are not affected.

Example The 20-bit value in R5 is subtracted from R6. If a carry occurs, the program continues at

label TONI.

SUBA R5,R6 ; R6 - R5 -> R6

JC TONI ; Carry occurred

... ; No carry

271

SLAU144J–December 2004–Revised July 2013 CPUX

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