Datasheet

0FFE0h
Interrupt Vector Table
Flash/ROM
RAM
16-Bit Peripheral Modules
8-Bit Peripheral Modules
Special Function Registers
0FFFFh
0FFDFh
0200h
01FFh
0100h
0FFh
010h
0Fh
0h
Word/Byte
Word/Byte
Word
Byte
Byte
Word/Byte
10000h
Flash/ROM
1FFFFh
Access
Word/Byte
www.ti.com Embedded Emulation
1.3 Embedded Emulation
Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no
additional system resources.
The benefits of embedded emulation include:
• Unobtrusive development and debug with full-speed execution, breakpoints, and single-steps in an
application are supported.
• Development is in-system subject to the same characteristics as the final application.
• Mixed-signal integrity is preserved and not subject to cabling interference.
1.4 Address Space
The MSP430 von-Neumann architecture has one address space shared with special function registers
(SFRs), peripherals, RAM, and Flash/ROM memory as shown in Figure 1-2. See the device-specific data
sheets for specific memory maps. Code access are always performed on even addresses. Data can be
accessed as bytes or words.
The addressable memory space is currently 128 KB.
Figure 1-2. Memory Map
1.4.1 Flash/ROM
The start address of Flash/ROM depends on the amount of Flash/ROM present and varies by device. The
end address for Flash/ROM is 0x0FFFF for devices with less that 60KB of Flash/ROM. Flash can be used
for both code and data. Word or byte tables can be stored and used in Flash/ROM without the need to
copy the tables to RAM before using them.
The interrupt vector table is mapped into the upper 16 words of Flash/ROM address space, with the
highest priority interrupt vector at the highest Flash/ROM word address (0x0FFFE).
25
SLAU144J–December 2004–Revised July 2013 Introduction
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