Datasheet

19 0

MSB

0000

LSB

19 0

MSB LSB

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Instruction Set Description

4.6.3.29 RRUM

RRUM.A Rotate right through carry the 20-bit CPU register content

RRUM.[W] Rotate right through carry the 16-bit CPU register content

RRUM.A #n,Rdst

Syntax 1 ≤ n ≤ 4

RRUM.W #n,Rdst or RRUM #n,Rdst

1 ≤ n ≤ 4

Operation 0 → MSB → MSB–1 ... LSB+1 → LSB → C

Description The destination operand is shifted right by one, two, three, or four bit positions as

shown in Figure 4-52. Zero is shifted into the MSB, the LSB is shifted into the carry bit.

RRUM works like an unsigned division by 2, 4, 8, or 16. The word instruction RRUM.W

clears the bits Rdst.19:16.

Note : This instruction does not use the extension word.

Status Bits N: Set if result is negative

.A: Rdst.19 = 1, reset if Rdst.19 = 0

.W: Rdst.15 = 1, reset if Rdst.15 = 0

Z: Set if result is zero, reset otherwise

C: Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3), or LSB+3 (n = 4)

V: Reset

Mode Bits OSCOFF, CPUOFF, and GIE are not affected.

Example The unsigned address-word in R5 is divided by 16.

RRUM.A #4,R5 ; R5 = R5 » 4. R5/16

Example The word in R6 is shifted right by one bit. The MSB R6.15 is loaded with 0.

RRUM.W #1,R6 ; R6 = R6/2. R6.19:15 = 0

Figure 4-52. Rotate Right Unsigned RRUM[.W] and RRUM.A

247

SLAU144J–December 2004–Revised July 2013 CPUX

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