Datasheet

19 0

MSB

LSB

19 0

MSB LSB

Instruction Set Description

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4.6.3.27 RRCM

RRCM.A Rotate right through carry the 20-bit CPU register content

RRCM.[W] Rotate right through carry the 16-bit CPU register content

RRCM.A #n,Rdst

Syntax 1 ≤ n ≤ 4

RRCM.W #n,Rdst or RRCM #n,Rdst

1 ≤ n ≤ 4

Operation C → MSB → MSB–1 ... LSB+1 → LSB → C

Description The destination operand is shifted right by one, two, three, or four bit positions as

shown in Figure 4-49. The carry bit C is shifted into the MSB, the LSB is shifted into the

carry bit. The word instruction RRCM.W clears the bits Rdst.19:16.

Note : This instruction does not use the extension word.

Status Bits N: Set if result is negative

.A: Rdst.19 = 1, reset if Rdst.19 = 0

.W: Rdst.15 = 1, reset if Rdst.15 = 0

Z: Set if result is zero, reset otherwise

C: Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3), or LSB+3 (n = 4)

V: Reset

Mode Bits OSCOFF, CPUOFF, and GIE are not affected.

Example The address-word in R5 is shifted right by three positions. The MSB–2 is loaded with 1.

SETC ; Prepare carry for MSB-2

RRCM.A #3,R5 ; R5 = R5 » 3 + 20000h

Example The word in R6 is shifted right by two positions. The MSB is loaded with the LSB. The

MSB–1 is loaded with the contents of the carry flag.

RRCM.W #2,R6 ; R6 = R6 » 2. R6.19:16 = 0

Figure 4-49. Rotate Right Through Carry RRCM[.W] and RRCM.A

244

CPUX SLAU144J–December 2004–Revised July 2013

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