Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TSSOP 28 16-Bit 16 MHz I/O number 24

ACLK

Bus

Conv.

Peripheral

MAB 16-Bit

MDB 16-Bit

MCLK

SMCLK

Clock

System

Peripheral Peripheral

Peripheral

Peripheral Peripheral Peripheral

Watchdog

RAM

Flash/

RISC CPU

16-Bit

JTAG/Debug

ACLK

SMCLK

ROM

MDB 8-Bit

JTAG

Architecture

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1.1 Architecture

The MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clock system that interconnect

using a von-Neumann common memory address bus (MAB) and memory data bus (MDB) (see Figure 1-

1). Partnering a modern CPU with modular memory-mapped analog and digital peripherals, the MSP430

offers solutions for demanding mixed-signal applications.

Key features of the MSP430x2xx family include:

• Ultralow-power architecture extends battery life

– 0.1 µA RAM retention

– 0.8 µA real-time clock mode

– 250 µA/MIPS active

• High-performance analog ideal for precision measurement

– Comparator-gated timers for measuring resistive elements

• 16-bit RISC CPU enables new applications at a fraction of the code size.

– Large register file eliminates working file bottleneck

– Compact core design reduces power consumption and cost

– Optimized for modern high-level programming

– Only 27 core instructions and seven addressing modes

– Extensive vectored-interrupt capability

• In-system programmable Flash permits flexible code changes, field upgrades and data logging

Figure 1-1. MSP430 Architecture

1.2 Flexible Clock System

The clock system is designed specifically for battery-powered applications. A low-frequency auxiliary clock

(ACLK) is driven directly from a common 32-kHz watch crystal. The ACLK can be used for a background

real-time clock self wake-up function. An integrated high-speed digitally controlled oscillator (DCO) can

source the master clock (MCLK) used by the CPU and high-speed peripherals. By design, the DCO is

active and stable in less than 2 µs at 1 MHz. MSP430-based solutions effectively use the high-

performance 16-bit RISC CPU in very short bursts.

• Low-frequency auxiliary clock = Ultralow-power stand-by mode

• High-speed master clock = High performance signal processing

Introduction SLAU144J–December 2004–Revised July 2013

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