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MDB Memory Data Bus

MSB Most-Significant Bit

MSD Most-Significant Digit

NMI (Non)-Maskable Interrupt See System Resets, Interrupts, and Operating Modes

PC Program Counter See RISC 16-Bit CPU

POR Power-On Reset See System Resets, Interrupts, and Operating Modes

PUC Power-Up Clear See System Resets, Interrupts, and Operating Modes

RAM Random Access Memory

SCG System Clock Generator See System Resets, Interrupts, and Operating Modes

SFR Special Function Register

SMCLK Sub-System Master Clock See Basic Clock Module

SP Stack Pointer See RISC 16-Bit CPU

SR Status Register See RISC 16-Bit CPU

src Source See RISC 16-Bit CPU

TOS Top-of-Stack See RISC 16-Bit CPU

WDT Watchdog Timer See Watchdog Timer

Each register is shown with a key indicating the accessibility of the each individual bit, and the initial

condition:

Key Bit Accessibility

rw Read/write

r Read only

r0 Read as 0

r1 Read as 1

w Write only

w0 Write as 0

w1 Write as 1

(w) No register bit implemented; writing a 1 results in a pulse.

The register bit is always read as 0.

h0 Cleared by hardware

h1 Set by hardware

-0,-1 Condition after PUC

-(0),-(1) Condition after POR

Read This First SLAU144J–December 2004–Revised July 2013

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