Datasheet

www.ti.com
7-1. Erase Modes.............................................................................................................. 312
7-2. Write Modes .............................................................................................................. 315
7-3. Flash Access While BUSY = 1 ......................................................................................... 320
7-4. Flash Memory Registers ................................................................................................ 323
8-1. PxSEL and PxSEL2 ..................................................................................................... 329
8-2. Digital I/O Registers ..................................................................................................... 333
9-1. SVS Registers............................................................................................................ 339
10-1. Watchdog Timer+ Registers............................................................................................ 346
11-1. OP1 Addresses........................................................................................................... 351
11-2. RESHI Contents.......................................................................................................... 351
11-3. SUMEXT Contents....................................................................................................... 351
11-4. Hardware Multiplier Registers .......................................................................................... 354
12-1. Timer Modes.............................................................................................................. 358
12-2. Output Modes ............................................................................................................ 364
12-3. Timer_A3 Registers...................................................................................................... 369
13-1. Timer Modes.............................................................................................................. 377
13-2. TBCLx Load Events ..................................................................................................... 383
13-3. Compare Latch Operating Modes ..................................................................................... 383
13-4. Output Modes ............................................................................................................ 384
13-5. Timer_B Registers ....................................................................................................... 390
14-1. USI Registers............................................................................................................. 405
14-2. Word Access to USI Registers ......................................................................................... 405
15-1. Receive Error Conditions ............................................................................................... 418
15-2. BITCLK Modulation Pattern ............................................................................................ 420
15-3. BITCLK16 Modulation Pattern ......................................................................................... 421
15-4. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0 ................................................ 424
15-5. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 1 ................................................ 425
15-6. USCI_A0 Control and Status Registers............................................................................... 428
15-7. USCI_A1 Control and Status Registers............................................................................... 428
16-1. UCxSTE Operation ...................................................................................................... 438
16-2. USCI_A0 and USCI_B0 Control and Status Registers ............................................................. 444
16-3. USCI_A1 and USCI_B1 Control and Status Registers ............................................................. 444
17-1. State Change Interrupt Flags........................................................................................... 465
17-2. USCI_B0 Control and Status Registers............................................................................... 467
17-3. USCI_B1 Control and Status Registers............................................................................... 467
18-1. Receive Error Conditions ............................................................................................... 480
18-2. Commonly Used Baud Rates, Baud Rate Data, and Errors ....................................................... 486
18-3. USART0 Control and Status Registers ............................................................................... 490
18-4. USART1 Control and Status Registers ............................................................................... 490
19-1. USART0 Control and Status Registers ............................................................................... 506
19-2. USART1 Control and Status Registers ............................................................................... 506
20-1. OA Output Configurations .............................................................................................. 514
20-2. OA Mode Select.......................................................................................................... 514
20-3. Two-Opamp Differential Amplifier Control Register Settings....................................................... 516
20-4. Two-Opamp Differential Amplifier Gain Settings..................................................................... 516
20-5. Three-Opamp Differential Amplifier Control Register Settings..................................................... 518
20-6. Three-Opamp Differential Amplifier Gain Settings................................................................... 518
20-7. OA Registers ............................................................................................................. 520
21-1. Comparator_A+ Registers .............................................................................................. 530
19
SLAU144J–December 2004–Revised July 2013 List of Tables
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated