Datasheet

Instruction Set Description

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4.6.2.13 CLRZ

* CLRZ Clear zero bit

CLRZ

Syntax

Operation 0 → Z

(.NOT.src .AND. dst → dst)

BIC #2,SR

Emulation

Description The constant 02h is inverted (0FFFDh) and logically ANDed with the destination

operand. The result is placed into the destination. The clear zero bit instruction is a word

instruction.

Status Bits N: Not affected

Z: Reset to 0

C: Not affected

V: Not affected

Mode Bits OSCOFF, CPUOFF, and GIE are not affected.

Example The zero bit in the SR is cleared.

CLRZ

Indirect, Auto-Increment mode: Call a subroutine at the 16-bit address contained in the

word pointed to by register R5 (20-bit address) and increment the 16-bit address in R5

afterwards by 2. The next time the software uses R5 as a pointer, it can alter the

program execution due to access to the next word address in the table pointed to by R5.

CALL @R5+ ; Start address at @R5. R5 + 2

Indexed mode: Call a subroutine at the 16-bit address contained in the 20-bit address

pointed to by register (R5 + X), for example, a table with addresses starting at X. The

address is within the lower 64KB. X is within +32KB.

CALL X(R5) ; Start address at @(R5+X). z16(R5)

176

CPUX SLAU144J–December 2004–Revised July 2013

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