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18-7. MSP430 Baud Rate Generator......................................................................................... 481
18-8. BITCLK Baud Rate Timing ............................................................................................. 482
18-9. Receive Error ............................................................................................................. 485
18-10. Transmit Interrupt Operation ........................................................................................... 487
18-11. Receive Interrupt Operation ............................................................................................ 487
18-12. Glitch Suppression, USART Receive Not Started ................................................................... 489
18-13. Glitch Suppression, USART Activated ................................................................................ 489
19-1. USART Block Diagram: SPI Mode .................................................................................... 498
19-2. USART Master and External Slave.................................................................................... 500
19-3. USART Slave and External Master.................................................................................... 501
19-4. Master Transmit Enable State Diagram............................................................................... 501
19-5. Slave Transmit Enable State Diagram ................................................................................ 502
19-6. SPI Master Receive-Enable State Diagram .......................................................................... 502
19-7. SPI Slave Receive-Enable State Diagram............................................................................ 502
19-8. SPI Baud Rate Generator............................................................................................... 503
19-9. USART SPI Timing ...................................................................................................... 503
19-10. Transmit Interrupt Operation ........................................................................................... 504
19-11. Receive Interrupt Operation ............................................................................................ 505
19-12. Receive Interrupt State Diagram....................................................................................... 505
20-1. OA Block Diagram ....................................................................................................... 513
20-2. Two-Opamp Differential Amplifier...................................................................................... 516
20-3. Two-Opamp Differential Amplifier OAx Interconnections ........................................................... 517
20-4. Three-Opamp Differential Amplifier.................................................................................... 518
20-5. Three-Opamp Differential Amplifier OAx Interconnections ......................................................... 519
21-1. Comparator_A+ Block Diagram ........................................................................................ 524
21-2. Comparator_A+ Sample-And-Hold .................................................................................... 526
21-3. RC-Filter Response at the Output of the Comparator............................................................... 527
21-4. Transfer Characteristic and Power Dissipation in a CMOS Inverter/Buffer ...................................... 527
21-5. Comparator_A+ Interrupt System...................................................................................... 528
21-6. Temperature Measurement System................................................................................... 528
21-7. Timing for Temperature Measurement Systems..................................................................... 529
22-1. ADC10 Block Diagram .................................................................................................. 535
22-2. Analog Multiplexer ....................................................................................................... 536
22-3. Sample Timing ........................................................................................................... 538
22-4. Analog Input Equivalent Circuit ........................................................................................ 538
22-5. Single-Channel Single-Conversion Mode............................................................................. 540
22-6. Sequence-of-Channels Mode .......................................................................................... 541
22-7. Repeat-Single-Channel Mode .......................................................................................... 542
22-8. Repeat-Sequence-of-Channels Mode................................................................................. 543
22-9. One-Block Transfer ...................................................................................................... 545
22-10. State Diagram for Data Transfer Control in One-Block Transfer Mode........................................... 546
22-11. Two-Block Transfer ...................................................................................................... 547
22-12. State Diagram for Data Transfer Control in Two-Block Transfer Mode........................................... 548
22-13. Typical Temperature Sensor Transfer Function ..................................................................... 550
22-14. ADC10 Grounding and Noise Considerations (Internal V
REF
) ...................................................... 550
22-15. ADC10 Grounding and Noise Considerations (External V
REF
) ..................................................... 551
22-16. ADC10 Interrupt System ................................................................................................ 551
23-1. ADC12 Block Diagram .................................................................................................. 561
23-2. Analog Multiplexer ....................................................................................................... 562
16
List of Figures SLAU144J–December 2004–Revised July 2013
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