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4.5.2.7.2 MSP430X Format I (Double-Operand) Instruction Cycles and Lengths
Table 4-18 lists the length and CPU cycles for all addressing modes of the MSP430X extended Format I
instructions.
Table 4-18. MSP430X Format I Instruction Cycles and Length
Addressing Mode No. of Cycles Length of Examples
Instruction
Source Destination .B/.W .A .B/.W/.A
Rn Rm
(1)
2 2 2 BITX.B R5,R8
PC 3 3 2 ADDX R9,PC
X(Rm) 5
(2)
7
(3)
3 ANDX.A R5,4(R6)
EDE 5
(2)
7
(3)
3 XORX R8,EDE
&EDE 5
(2)
7
(3)
3 BITX.W R5,&EDE
@Rn Rm 3 4 2 BITX @R5,R8
PC 3 4 2 ADDX @R9,PC
X(Rm) 6
(2)
9
(3)
3 ANDX.A @R5,4(R6)
EDE 6
(2)
9
(3)
3 XORX @R8,EDE
&EDE 6
(2)
9
(3)
3 BITX.B @R5,&EDE
@Rn+ Rm 3 4 2 BITX @R5+,R8
PC 4 5 2 ADDX.A @R9+,PC
X(Rm) 6
(2)
9
(3)
3 ANDX @R5+,4(R6)
EDE 6
(2)
9
(3)
3 XORX.B @R8+,EDE
&EDE 6
(2)
9
(3)
3 BITX @R5+,&EDE
#N Rm 3 3 3 BITX #20,R8
PC
(4)
4 4 3 ADDX.A #FE000h,PC
X(Rm) 6
(2)
8
(3)
4 ANDX #1234,4(R6)
EDE 6
(2)
8
(3)
4 XORX #A5A5h,EDE
&EDE 6
(2)
8
(3)
4 BITX.B #12,&EDE
X(Rn) Rm 4 5 3 BITX 2(R5),R8
PC
(4)
5 6 3 SUBX.A 2(R6),PC
X(Rm) 7
(2)
10
(3)
4 ANDX 4(R7),4(R6)
EDE 7
(2)
10
(3)
4 XORX.B 2(R6),EDE
&EDE 7
(2)
10
(3)
4 BITX 8(SP),&EDE
EDE Rm 4 5 3 BITX.B EDE,R8
PC
(4)
5 6 3 ADDX.A EDE,PC
X(Rm) 7
(2)
10
(3)
4 ANDX EDE,4(R6)
EDE 7
(2)
10
(3)
4 ANDX EDE,TONI
&TONI 7
(2)
10
(3)
4 BITX EDE,&TONI
&EDE Rm 4 5 3 BITX &EDE,R8
PC
(4)
5 6 3 ADDX.A &EDE,PC
X(Rm) 7
(2)
10
(3)
4 ANDX.B &EDE,4(R6)
TONI 7
(2)
10
(3)
4 XORX &EDE,TONI
&TONI 7
(2)
10
(3)
4 BITX &EDE,&TONI
(1)
Repeat instructions require n + 1 cycles, where n is the number of times the instruction is executed.
(2)
Reduce the cycle count by one for MOV, BIT, and CMP instructions.
(3)
Reduce the cycle count by two for MOV, BIT, and CMP instructions.
(4)
Reduce the cycle count by one for MOV, ADD, and SUB instructions.
158
CPUX SLAU144J–December 2004–Revised July 2013
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