Datasheet

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 19:16
Operand LSBs 15:0
0.......................................................................................
Address
Address+2
15 14 13 12 11 10 9 8 7 6 5 4 3 0
0 0 0 1 1 0 A/L n-1/Rn
Op-code B/W dst
0 ZC # 0 0
src 0 0 0
0 0 0 1 1 A/L
Op-code B/W dst
src.15:0
src.19:16 0 0
src Ad As
0 0 0 1 1 A/L
Op-code B/W dst
dst.15:0
0 0
src Ad
0 0 0 1 1 A/L dst.19:16
Op-code B/W dst
src.15:0
0 0
src Ad
0 0 0 0
dst.19:16
0 0 0 0
As
src.19:16
As
dst.15:0
MSP430 and MSP430X Instructions www.ti.com
The four possible addressing combinations for the extension word for Format I instructions are shown in
Figure 4-28.
Figure 4-28. Extended Format I Instruction Formats
If the 20-bit address of a source or destination operand is located in memory, not in a CPU register, then
two words are used for this operand as shown in Figure 4-29.
Figure 4-29. 20-Bit Addresses in Memory
152
CPUX SLAU144J–December 2004–Revised July 2013
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