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13-8. Up/Down Mode Flag Setting............................................................................................ 380
13-9. Output Unit in Up/Down Mode ......................................................................................... 381
13-10. Capture Signal (SCS = 1)............................................................................................... 381
13-11. Capture Cycle ............................................................................................................ 382
13-12. Output Example, Timer in Up Mode ................................................................................... 385
13-13. Output Example, Timer in Continuous Mode......................................................................... 386
13-14. Output Example, Timer in Up/Down Mode ........................................................................... 387
13-15. Capture/Compare TBCCR0 Interrupt Flag............................................................................ 388
14-1. USI Block Diagram: SPI Mode ......................................................................................... 397
14-2. USI Block Diagram: I
2
C Mode .......................................................................................... 398
14-3. SPI Timing ................................................................................................................ 400
14-4. Data Adjustments for 7-Bit SPI Data .................................................................................. 401
15-1. USCI_Ax Block Diagram: UART Mode (UCSYNC = 0)............................................................. 412
15-2. Character Format ........................................................................................................ 413
15-3. Idle-Line Format.......................................................................................................... 414
15-4. Address-Bit Multiprocessor Format.................................................................................... 415
15-5. Auto Baud Rate Detection - Break/Synch Sequence ............................................................... 416
15-6. Auto Baud Rate Detection - Synch Field ............................................................................. 416
15-7. UART vs IrDA Data Format............................................................................................. 417
15-8. Glitch Suppression, USCI Receive Not Started...................................................................... 419
15-9. Glitch Suppression, USCI Activated................................................................................... 419
15-10. BITCLK Baud Rate Timing With UCOS16 = 0 ....................................................................... 420
15-11. Receive Error ............................................................................................................. 423
16-1. USCI Block Diagram: SPI Mode ....................................................................................... 437
16-2. USCI Master and External Slave ...................................................................................... 439
16-3. USCI Slave and External Master ...................................................................................... 440
16-4. USCI SPI Timing with UCMSB = 1 .................................................................................... 442
17-1. USCI Block Diagram: I
2
C Mode ........................................................................................ 451
17-2. I
2
C Bus Connection Diagram ........................................................................................... 452
17-3. I
2
C Module Data Transfer ............................................................................................... 452
17-4. Bit Transfer on the I
2
C Bus ............................................................................................. 453
17-5. I
2
C Module 7-Bit Addressing Format ................................................................................. 453
17-6. I
2
C Module 10-Bit Addressing Format................................................................................. 453
17-7. I
2
C Module Addressing Format with Repeated START Condition................................................. 454
17-8. I
2
C Time Line Legend ................................................................................................... 454
17-9. I
2
C Slave Transmitter Mode ............................................................................................ 455
17-10. I
2
C Slave Receiver Mode ............................................................................................... 457
17-11. I
2
C Slave 10-bit Addressing Mode ..................................................................................... 458
17-12. I
2
C Master Transmitter Mode ........................................................................................... 460
17-13. I
2
C Master Receiver Mode .............................................................................................. 462
17-14. I
2
C Master 10-bit Addressing Mode ................................................................................... 463
17-15. Arbitration Procedure Between Two Master Transmitters.......................................................... 463
17-16. Synchronization of Two I
2
C Clock Generators During Arbitration ................................................. 464
18-1. USART Block Diagram: UART Mode ................................................................................. 476
18-2. Character Format ........................................................................................................ 477
18-3. Idle-Line Format.......................................................................................................... 478
18-4. Address-Bit Multiprocessor Format.................................................................................... 479
18-5. State Diagram of Receiver Enable .................................................................................... 480
18-6. State Diagram of Transmitter Enable ................................................................................. 481
15
SLAU144J–December 2004–Revised July 2013 List of Figures
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