Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TSSOP 28 16-Bit 16 MHz I/O number 24

141

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144

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147

148

149

150

15 12 11 10 9 8 7 6 5 4 3 0

0001

1 00 ZC # A/L 0 0 (n-1)/Rn

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MSP430 and MSP430X Instructions

Table 4-10. MSP430 Format I Instructions Cycles and Length (continued)

Addressing Mode

Length of

No. of Cycles Example

Instruction

Src Dst

Rm 3 2 AND EDE,R6

PC 3 2 BR EDE

EDE TONI 6

(1)

3 CMP EDE,TONI

x(Rm) 6

(1)

3 MOV EDE,0(SP)

&TONI 6

(1)

3 MOV EDE,&TONI

Rm 3 2 MOV &EDE,R8

PC 3 2 BR &EDE

&EDE TONI 6

(1)

3 MOV &EDE,TONI

x(Rm) 6

(1)

3 MOV &EDE,0(SP)

&TONI 6

(1)

3 MOV &EDE,&TONI

4.5.2 MSP430X Extended Instructions

The extended MSP430X instructions give the MSP430X CPU full access to its 20-bit address space. Most

MSP430X instructions require an additional word of op-code called the extension word. Some extended

instructions do not require an additional word and are noted in the instruction description. All addresses,

indexes, and immediate numbers have 20-bit values when preceded by the extension word.

There are two types of extension words:

• Register/register mode for Format I instructions and register mode for Format II instructions

• Extension word for all other address mode combinations

4.5.2.1 Register Mode Extension Word

The register mode extension word is shown in Figure 4-24 and described in Table 4-11. An example is

shown in Figure 4-26.

Figure 4-24. Extension Word for Register Modes

Table 4-11. Description of the Extension Word Bits for Register Mode

Bit Description

15:11 Extension word op-code. Op-codes 1800h to 1FFFh are extension words.

10:9 Reserved

ZC Zero carry

0 The executed instruction uses the status of the carry bit C.

1 The executed instruction uses the carry bit as 0. The carry bit is defined by the result of the final operation after

instruction execution.

# Repetition

0 The number of instruction repetitions is set by extension word bits 3:0.

1 The number of instruction repetitions is defined by the value of the four LSBs of Rn. See description for bits 3:0.

147

SLAU144J–December 2004–Revised July 2013 CPUX

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