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MSP430 and MSP430X Instructions www.ti.com
Table 4-9. MSP430 Format II Instruction Cycles and Length (continued)
No. of Cycles
Length of
Addressing Mode Example
RRA, RRC
Instruction
PUSH CALL
SWPB, SXT
#N N/A 3
(1)
4
(2)
2
CALL #LABEL
X(Rn) 4 4
(2)
4
(2)
2
CALL 2(R7)
EDE 4 4
(2)
4
(2)
2
PUSH EDE
&EDE 4 4
(2)
4
(2)
2
SXT &EDE
4.5.1.5.3 Jump Instructions Cycles and Lengths
All jump instructions require one code word and take two CPU cycles to execute, regardless of whether
the jump is taken or not.
4.5.1.5.4 Format I (Double-Operand) Instruction Cycles and Lengths
Table 4-10 lists the length and CPU cycles for all addressing modes of the MSP430 Format I instructions.
Table 4-10. MSP430 Format I Instructions Cycles and Length
Addressing Mode
Length of
No. of Cycles Example
Instruction
Src Dst
Rm 1 1 MOV R5,R8
PC 2 1 BR R9
Rn x(Rm) 4
(1)
2 ADD R5,4(R6)
EDE 4
(1)
2 XOR R8,EDE
&EDE 4
(1)
2 MOV R5,&EDE
Rm 2 1 AND @R4,R5
PC 3 1 BR @R8
@Rn x(Rm) 5
(1)
2 XOR @R5,8(R6)
EDE 5
(1)
2 MOV @R5,EDE
&EDE 5
(1)
2 XOR @R5,&EDE
Rm 2 1 ADD @R5+,R6
PC 3 1 BR @R9+
@Rn+ x(Rm) 5
(1)
2 XOR @R5,8(R6)
EDE 5
(1)
2 MOV @R9+,EDE
&EDE 5
(1)
2 MOV @R9+,&EDE
Rm 2 2 MOV #20,R9
PC 3 2 BR #2AEh
#N x(Rm) 5
(1)
3 MOV #0300h,0(SP)
EDE 5
(1)
3 ADD #33,EDE
&EDE 5
(1)
3 ADD #33,&EDE
Rm 3 2 MOV 2(R5),R7
PC 3 2 BR 2(R6)
x(Rn) TONI 6
(1)
3 MOV 4(R7),TONI
x(Rm) 6
(1)
3 ADD 4(R4),6(R9)
&TONI 6
(1)
3 MOV 2(R4),&TONI
(1)
MOV, BIT, and CMP instructions execute in one fewer cycle.
146
CPUX SLAU144J–December 2004–Revised July 2013
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