Datasheet

15
Op-Code
13 12 10 9 8 0
Condition S 10-Bit Signed PC Offset
MSP430 and MSP430X Instructions www.ti.com
4.5.1.3 Jump Instructions
Figure 4-23 shows the format for MSP430 and MSP430X jump instructions. The signed 10-bit word offset
of the jump instruction is multiplied by two, sign-extended to a 20-bit address, and added to the 20-bit PC.
This allows jumps in a range of –511 to +512 words relative to the PC in the full 20-bit address space.
Jumps do not affect the status bits. Table 4-6 lists and describes the eight jump instructions.
Figure 4-23. Format of Conditional Jump Instructions
Table 4-6. Conditional Jump Instructions
Mnemonic S-Reg, D-Reg Operation
JEQ/JZ Label Jump to label if zero bit is set
JNE/JNZ Label Jump to label if zero bit is reset
JC Label Jump to label if carry bit is set
JNC Label Jump to label if carry bit is reset
JN Label Jump to label if negative bit is set
JGE Label Jump to label if (N .XOR. V) = 0
JL Label Jump to label if (N .XOR. V) = 1
JMP Label Jump to label unconditionally
4.5.1.4 Emulated Instructions
In addition to the MSP430 and MSP430X instructions, emulated instructions are instructions that make
code easier to write and read, but do not have op-codes themselves. Instead, they are replaced
automatically by the assembler with a core instruction. There is no code or performance penalty for using
emulated instructions. The emulated instructions are listed in Table 4-7.
Table 4-7. Emulated Instructions
Status Bits
(1)
Instruction Explanation Emulation
V N Z C
Add Carry to dst * * * *
ADC(.B) dst ADDC(.B) #0,dst
MOV
Branch indirectly dst – – – –
BR dst
dst,PC
Clear dst – – – –
CLR(.B) dst MOV(.B) #0,dst
BIC
Clear Carry bit – – – 0
CLRC
#1,SR
BIC
Clear Negative bit – 0 – –
CLRN
#4,SR
BIC
Clear Zero bit – – 0 –
CLRZ
#2,SR
Add Carry to dst decimally * * * *
DADC(.B) dst DADD(.B) #0,dst
Decrement dst by 1 * * * *
DEC(.B) dst SUB(.B) #1,dst
Decrement dst by 2 * * * *
DECD(.B) dst SUB(.B) #2,dst
Disable interrupt – – – –
DINT BIC #8,SR
Enable interrupt – – – –
EINT BIS #8,SR
Increment dst by 1 * * * *
INC(.B) dst ADD(.B) #1,dst
Increment dst by 2 * * * *
INCD(.B) dst ADD(.B) #2,dst
(1)
* = Status bit is affected; – = Status bit is not affected; 0 = Status bit is cleared; 1 = Status bit is set.
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CPUX SLAU144J–December 2004–Revised July 2013
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