Datasheet

xxxxh
Address
Space
2100h
8346h
PC
1103Ah
11038h
11036h
23456h
15678h
R5
R6
15678h
+02100h
17778h
Register
Before:
Address
Space
Register
After:
5596h
11034h
xxxxh
2100h
8346h
PC1103Ah
11038h
11036h
23456h
15678h
R5
R6
5596h
11034h
xxxxh
2345h
1777Ah
17778h
xxxxh
7777h
1777Ah
17778h
05432h
+02345h
07777h
src
dst
Sum
23456h
+F8346h
1B79Ch
xxxxh
5432h
1B79Eh
1B79Ch
xxxxh
5432h
1B79Eh
1B79Ch
Addressing Modes www.ti.com
4.4.2.3 MSP430X Instruction With Indexed Mode
When using an MSP430X instruction with Indexed mode, the operand can be located anywhere in the
range of Rn + 19 bits.
Length: Three or four words
Operation: The operand address is the sum of the 20-bit CPU register content and the 20-bit
index. The 4 MSBs of the index are contained in the extension word; the 16 LSBs
are contained in the word following the instruction. The CPU register is not modified
Comment: Valid for source and destination. The assembler calculates the register index and
inserts it.
ADDX.A 12346h(R5),32100h(R6) ;
Example:
This instruction adds the 20-bit data contained in the source and the destination
addresses and places the result into the destination.
Source: Two words pointed to by R5 + 12346h which results in address 23456h + 12346h =
3579Ch.
Destination: Two words pointed to by R6 + 32100h which results in address 45678h + 32100h =
77778h.
130
CPUX SLAU144J–December 2004–Revised July 2013
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