Datasheet

FFFFF

0000C

Lower 64 KB

0,FFFF

10000

Rn.19:0

±32 KB

Rn.19:0

±32 KB

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Addressing Modes

Figure 4-17. Overflow and Underflow for Indexed Mode

Length: Two or three words

Operation: The sign-extended 16-bit index in the next word after the instruction is added to the

20 bits of the CPU register Rn. This delivers a 20-bit address, which points to an

address in the range 0 to FFFFFh. The operand is the content of the addressed

memory location.

Comment: Valid for source and destination. The assembler calculates the register index and

inserts it.

ADD.W 8346h(R5),2100h(R6) ;

Example:

This instruction adds the 16-bit data contained in the source and the destination

addresses and places the 16-bit result into the destination. Source and destination

operand can be located in the entire address range.

Source: The word pointed to by R5 + 8346h. The negative index 8346h is sign extended,

which results in address 23456h + F8346h = 1B79Ch.

Destination: The word pointed to by R6 + 2100h results in address 15678h + 2100h = 17778h.

129

SLAU144J–December 2004–Revised July 2013 CPUX

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