Datasheet

High Byte Low Byte
Register - Ad dress-Word Operation
Register
Memory
Operation
Memory
Unused
0
Memory +2
Memory +2
19 16 15 0
8 7
High Byte Low Byte
Word-Register Operation
Register
Memory
Operation
0
Register
Un-
used
19 16 15 0
8 7
CPU Registers www.ti.com
Figure 4-12. Word-Register Operation
Figure 4-13 and Figure 4-14 show 20-bit address-word handling (.A suffix). The handling is shown for a
source register and a destination memory address-word and for a source memory address-word and a
destination register.
Figure 4-13. Register – Address-Word Operation
124
CPUX SLAU144J–December 2004–Revised July 2013
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated