Datasheet

High Byte Low Byte
Register-Word Operation
Register
Memory
Operation
Memory
Un-
used
19 16 15 0
8 7
Unused
High Byte Low Byte
Register-Byte Operation
High Byte Low Byte
Byte-Register Operation
Register
Memory Register
Memory
Operation
Memory
Operation
0 Register
Unused
Un-
used
0
19 16 15 0
19 16 15 0
8 7
8 7
Un-
used
www.ti.com CPU Registers
4.3.5 General-Purpose Registers (R4 to R15)
The 12 CPU registers (R4 to R15) contain 8-bit, 16-bit, or 20-bit values. Any byte-write to a CPU register
clears bits 19:8. Any word-write to a register clears bits 19:16. The only exception is the SXT instruction.
The SXT instruction extends the sign through the complete 20-bit register.
The following figures show the handling of byte, word, and address-word data. Note the reset of the
leading most significant bits (MSBs) if a register is the destination of a byte or word instruction.
Figure 4-10 shows byte handling (8-bit data, .B suffix). The handling is shown for a source register and a
destination memory byte and for a source memory byte and a destination register.
Figure 4-10. Register-Byte/Byte-Register Operation
Figure 4-11 and Figure 4-12 show 16-bit word handling (.W suffix). The handling is shown for a source
register and a destination memory word and for a source memory word and a destination register.
Figure 4-11. Register-Word Operation
123
SLAU144J–December 2004–Revised July 2013 CPUX
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated