Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TSSOP 28 16-Bit 16 MHz I/O number 24

121

122

123

124

125

126

127

128

129

130

SCG0 GIE Z C

rw-0

15 0

Reserved

CPU

OFF

OSC

OFF

SCG1V

8 79

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CPU Registers

4.3.3 Status Register (SR)

The 16-bit SR (SR/R2), used as a source or destination register, can only be used in register mode

addressed with word instructions. The remaining combinations of addressing modes are used to support

the constant generator. Figure 4-9 shows the SR bits. Do not write 20-bit values to the SR. Unpredictable

operation can result.

Figure 4-9. SR Bits

Table 4-1 describes the SR bits.

Table 4-1. SR Bit Description

Bit Description

Reserved Reserved

V Overflow. This bit is set when the result of an arithmetic operation overflows the signed-variable range.

Set when:

ADD(.B), ADDX(.B,.A), ADDC(.B),

positive + positive = negative

ADDCX(.B.A), ADDA

negative + negative = positive

otherwise reset

Set when:

SUB(.B), SUBX(.B,.A), SUBC(.B),

positive – negative = negative

SUBCX(.B,.A), SUBA, CMP(.B),

negative – positive = positive

CMPX(.B,.A), CMPA

otherwise reset

SCG1 System clock generator 1. This bit may be to enable/disable functions in the clock system depending on the device

family; for example, DCO bias enable/disable

SCG0 System clock generator 0. This bit may be used to enable/disable functions in the clock system depending on the

device family; for example, FLL disable/enable

OSCOFF Oscillator off. This bit, when set, turns off the LFXT1 crystal oscillator when LFXT1CLK is not used for MCLK or

SMCLK.

CPUOFF CPU off. This bit, when set, turns off the CPU.

GIE General interrupt enable. This bit, when set, enables maskable interrupts. When reset, all maskable interrupts are

disabled.

N Negative. This bit is set when the result of an operation is negative and cleared when the result is positive.

Z Zero. This bit is set when the result of an operation is 0 and cleared when the result is not 0.

C Carry. This bit is set when the result of an operation produced a carry and cleared when no carry occurred.

121

SLAU144J–December 2004–Revised July 2013 CPUX

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