Datasheet
Direction
0: Input
1: Output
P2SEL.7
P2DIR.7
P2IN.7
P2IRQ.7
D
EN
Module X IN
Module X OUT
P2OUT.7
Interrupt
Edge Select
Q
EN
Set
P2SEL.7
P2IES.7
P2IFG.7
P2IE.7
DVSS
DVCC
Pad Logic
1
1
0
1
0
1
0
Bus
Keeper
EN
P2.7/XOUT/CA7
1
0
LFXT1CLK
P2.6/XIN/CA6
LFXT1 off
BCSCTL3.LFXT1Sx = 11
From P2.6/XIN
From
Comparator
To Comparator
P2SEL.6
CAPD.7
P2REN.7
MSP430F21x2
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SLAS578J –NOVEMBER 2007– REVISED JANUARY 2012
Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger
Table 27. Port P2 (P2.7) Pin Functions
CONTROL BITS / SIGNALS
(1)
PIN NAME (P2.x) x FUNCTION
P2SEL.7
CAPD.7 P2DIR.7
P2SEL2.x = 0
P2.7 (I/O) 0 I: 0, O: 1 0
P2.7/XOUT/CA7 7 XOUT (default) X 1 1
CA7
(2)
1 X 0
(1) X = Don't care
(2) Setting the CAPD.x bit disables the output driver as well as the input to prevent parasitic cross currents when applying analog signals.
Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin, regardless
of the state of the associated CAPD.x bit.
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