Datasheet

To JTAG
From JTAG
Direction
0: Input
1: Output
P1SEL.x
P1DIR.x
P1IN.x
P1IRQ.x
D
EN
Module X In
Module X Out
P1OUT.x
Interrupt
Edge Select
Q
EN
Set
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x
DVSS
DVCC
P1REN.x
Pad Logic
1
1
0
0
1
1
0
Bus
Keeper
EN
P1.5/TA0.0/TMS
P1.6/TA0.1/TCLK
P1.7/TA0.2/TDO/TDI
MSP430F21x2
SLAS578J –NOVEMBER 2007– REVISED JANUARY 2012 www.ti.com
Port P1 Pin Schematic: P1.5 to P1.7
Table 21. Port P1 (P1.5 to P1.7) Pin Functions
CONTROL BITS / SIGNALS
(1)
PIN NAME (P1.x) x FUNCTION
P1SEL.x
P1DIR.x JTAG Mode
P1SEL2.x=0
P1.5 (I/O) I: 0; O: 1 0 0
P1.5/TA0.0/TMS 5 Timer0_A3.TA0 1 1 0
TMS
(2)
X X 1
P1.6 (I/O) I: 0; O: 1 0 0
P1.6/TA0.1/TDI/TCLK 6 Timer0_A3.TA1 1 1 0
TDI/TCLK
(2)
X X 1
P1.6 (I/O) I: 0; O: 1 0 0
P1.7/TA0.2/TDO/TDI 7 Timer0_A3.TA2 1 1 0
TDO/TDI
(2)
X X 1
(1) X = Don't care
(2) In JTAG mode, the internal pullup/pulldown resistors are disabled.
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