Datasheet

To JTAG
From JTAG
Direction
0: Input
1: Output
P1SEL.4
P1DIR.4
P1IN.4
P1IRQ.4
Module X IN
SMCLK
P1OUT.x
Interrupt
Edge Select
Q
EN
Set
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x
DVSS
DVCC
P1REN.4
Pad Logic
1
1
0
0
1
1
0
Bus
Keeper
EN
P1.4/SMCLK/TCK
D
EN
MSP430F21x2
www.ti.com SLAS578J –NOVEMBER 2007– REVISED JANUARY 2012
Port P1 Pin Schematic: P1.4
Table 20. Port P1 (P1.4) Pin Functions
CONTROL BITS / SIGNALS
(1)
PIN NAME (P1.x) x FUNCTION
P1SEL.x
P1DIR.x JTAG Mode
P1SEL2.x=0
P1.4 (I/O) I: 0; O: 1 0 0
P1.4/SMCLK/TCK 4 SMCLK 1 1 0
TCK
(2)
X X 1
(1) X = Don't care
(2) In JTAG mode, the internal pullup/pulldown resistors are disabled.
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