Datasheet

MSP430F21x2
SLAS578J –NOVEMBER 2007– REVISED JANUARY 2012 www.ti.com
Timer0_A3
Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 14. Timer0_A3 Signal Connections
INPUT PIN NUMBER MODULE OUTPUT PIN NUMBER
DEVICE INPUT MODULE MODULE
OUTPUT
SIGNAL INPUT NAME BLOCK
PW RHB, RTV PW RHB, RTV
SIGNAL
21 - P1.0 21 - P1.0 TACLK TACLK Timer NA
ACLK ACLK
SMCLK SMCLK
9 - P2.1 7 - P2.1 TAINCLK INCLK
22 - P1.1 22 - P1.1 TA0 CCI0A CCR0 TA0 22 - P1.1 22 - P1.1
10 - P2.2 8 - P2.2 TA0 CCI0B 26 - P1.5 26 - P1.5
DV
SS
GND 10 - P2.2 8 - P2.2
ADC10 ADC10
DV
CC
V
CC
(internal) (internal)
23 - P1.2 23 - P1.2 TA1 CCI1A CCR1 TA1 23 - P1.2 23 - P1.2
CAOUT
CCI1B 27 - P1.6 27 - P1.6
(internal)
DV
SS
GND 19 - P2.3 18 - P2.3
ADC10 ADC10
DV
CC
V
CC
(internal) (internal)
24 - P1.3 24 - P1.3 TA2 CCI2A CCR2 TA2 24 - P1.3 24 - P1.3
ACLK (internal) CCI2B 28 - P1.7 28 - P1.7
DV
SS
GND 20 - P2.4 19 - P2.4
ADC10 ADC10
DV
CC
V
CC
(internal) (internal)
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