Datasheet

MSP430F21x1

SLAS439F –SEPTEMBER 2004– REVISED AUGUST 2011

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Timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Table 14. Timer_A3 Signal Connections

INPUT PIN NUMBER MODULE OUTPUT PIN NUMBER

DEVICE INPUT MODULE MODULE

OUTPUT

SIGNAL INPUT NAME BLOCK

DW, PW, DGV RGE DW, PW, DGV RGE

SIGNAL

13 - P1.0 13 - P1.0 TACLK TACLK

ACLK ACLK

Timer NA

SMCLK SMCLK

9 - P2.1 7 - P2.1 INCLK INCLK

14 - P1.1 14 - P1.1 TA CCI0A 14 - P1.1 14 - P1.1

10 - P2.2 8 - P2.2 TA CCI0B 18 - P1.5 18 - P1.5

CCR0 TA

VSS GND

VCC VCC

15 - P1.2 15 - P1.2 TA1 CCI1A 11 - P2.3 10 - P2.3

CAOUT

CCI1B 15 - P1.2 15 - P1.2

(internal)

CCR1 TA1

VSS GND 19 - P1.6 20 - P1.6

VCC VCC

16 - P1.3 16 - P1.3 TA2 CCI2A 12 - P2.4 11 - P2.4

ACLK (internal) CCI2B 16 - P1.3 16 - P1.3

CCR2 TA2

VSS GND 20 - P1.7 21 - P1.7

VCC VCC