Datasheet

MSP430F2013-EP
www.ti.com SLAS774A –JULY 2011– REVISED OCTOBER 2011
Absolute Maximum Ratings
(1)
Voltage applied at V
CC
to V
SS
-0.3 V to 4.1 V
Voltage applied to any pin
(2)
-0.3 V to V
CC
+ 0.3 V
Diode current at any device terminal ±2 mA
Unprogrammed device -55°C to 150°C
T
stg
Storage temperature
(3)
Programmed device -40°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V
SS
. The JTAG fuse-blow voltage, V
FB
, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
THERMAL INFORMATION
MSP430F2013-EP
THERMAL METRIC
(1)
RSA UNITS
16 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
38.1
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
26
θ
JB
Junction-to-board thermal resistance
(4)
7.5
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
0.3
ψ
JB
Junction-to-board characterization parameter
(6)
5.7
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
1.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Recommended Operating Conditions
MIN NOM MAX UNIT
During program execution 1.8 3.6
V
CC
Supply voltage V
During flash program/erase 2.2 3.6
V
SS
Supply voltage 0 V
T
A
Operating free-air temperature -40 125 °C
V
CC
= 1.8 V,
dc 6
Duty cycle = 50% ± 10%
V
CC
= 2.7 V,
f
SYSTEM
Processor frequency (maximum MCLK frequency)
(1)(2)
dc 12 MHz
Duty cycle = 50% ± 10%
V
CC
≥ 3.3 V,
dc 16
Duty cycle = 50% ± 10%
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
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