Datasheet

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SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005
63
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Port P1 (P1.7) pin schematics, MSP430x20x2
ADC10AE.7
Pad Logic
INCHx = 7
A7
Bus
Keeper
EN
Direction
0: Input
1: Output
1
0
P1DIR.7
P1IN.7
P1IRQ.7
D
EN
Module X IN
1
0
Module X OUT
P1OUT.7
Interrupt
Edge
Select
Q
EN
Set
P1SEL.7
P1IES.7
P1IFG.7
P1IE.7
P1.7/SDI/SDA/A7/TDO/TDI
1
0
DVSS
DVCC
P1REN.7
P1SEL.7
USIPE7
USI Module Direction
From JTAG
From JTAG (TDO)
USI Module Output
1
To JTAG
From JTAG
(I
2
C Mode)