Datasheet

  
  
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005
60
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1 (P1.4) pin schematics, MSP430x20x2
Bus
Keeper
EN
Direction
0: Input
1: Output
P1SEL.4
1
0
P1DIR.4
P1IRQ.4
D
EN
Module X IN
1
0
Module X OUT
P1OUT.4
Interrupt
Edge
Select
Q
EN
Set
P1SEL.4
P1IES.4
P1IFG.4
P1IE.4
P1.4/SMCLK/A4/VREF+/VeREF+/TCK
1
0
DVSS
DVCC
P1REN.4
To JTAG
From JTAG
1
ADC10AE.4
Pad Logic
INCHx = 4
A4
To/from ADC10
positive reference